1. Technical Field
The present subject matter generally relates to semiconductor integrated circuits, and more particularly, to charge pump arrays in memory devices utilizing three-dimensional circuit techniques.
2. Background Art
Certain semiconductor integrated circuits (ICs), including certain types of memory devices, may include charge pump arrays to create voltages for internal use that are different than the voltages provided at the power inputs of the IC. Various designs for charge pump arrays are well known in the art and may include capacitors to store charge at different stages within the charge pump arrays. Additional capacitors may be used as bypass capacitors on the output of the charge pump array to reduce noise on the output. In some cases, multiple charge pump arrays may be ganged in parallel, with their outputs coupled together, to provide higher current capability and multiple bypass capacitors may also be included in parallel to increase the capacitance on the ganged charge pump array outputs. Higher currents may lead to higher values of capacitance in the capacitors in the charge pump arrays and/or the bypass capacitors.
Some ICs, including dedicated memory devices, include blocks of memory cells. While traditional memory devices organize the cells in a two dimensional array, some devices may build a three dimensional array of cells. In some three dimensional flash memories, a NAND string may be built vertically, stacking the individual field-effect transistors (FETs) of the string on top of each other, so that the string extends out from the substrate. Such architectures may provide for very high bit densities in a flash memory device. A side-effect of these large three dimensional structures is that capacitance of the control lines may be higher than those of many two dimensional memory structures. The higher capacitance of the control lines may lead to higher current drawn from the charge pump arrays in the IC, in some cases.